Power-aware test optimization for core-based 3D-SOCs under TSV-constraints

Abstract

While 3D chips open up versatile potentialities in compact system design, they pose the challenge of testing the composite system, which consists of multiple cores, logic, and memory, interconnected across different layers of the chip. The test strategy for such chips must also take into account the issues of inherent power and thermal constraints, design of test-access mechanism (TAM), and the decision concerning pre-bond and post-bond test choices. Additionally, for post-bond testing, the constraints imposed by the limited use of TSVs, worsen the controllability and observability of the cores that are accessed through the inter-layer scan-paths. Thus, while designing the TAM architecture, the optimization of overall test time under the constraints of power and TSV-count, is needed. This paper presents a new technique for test-time reduction in post-bond core-based 3D-SOCs, considering certain constraints on test power and TAM width (i.e., bounds on TSVs). The proposed algorithm runs much faster compared to prior art, and our results on several ITC02 benchmarks reveal significant reduction in test-time for most of the cases.