Abstract
A low power seven transistors (7T) dual threshold voltage (dual-Vt) SRAM cell in 65nm CMOS technology is presented. Using the conventional dual-Vt 7T structure, reduces both read/write and standby (leakage) power consumption significantly compared to the conventional 6T SRAM cell. In order to reduce the leakage power consumption even further, a forward body biasing (FBB) technique was used for the stacked read transistors. This optimization resulted in significant reduction in standby and a slight reduction in write power dissipation.
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