Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization

Abstract

This paper presents comprehensive analyses of power-performance tradeoffs in current-mode logic (CML)-based transmitters via equation-based optimization and provides practical design guidelines that can help achieving optimum power efficiency. An accurate equation-based optimization framework was developed for this purpose, and using this framework, key circuit-level design parameters were found with specific design specifications and process technologies. The proposed optimization framework can determine optimum clock edge-rate (i.e., ratio of rise/fall time to clock period) and inter-stage voltage swings that enable significant power savings without affecting performance. Various transmitter design tradeoffs were analyzed for 45-nm, 65-nm, and 90-nm technologies considering data rate, clock edge-rate, and inter-stage swing optimization. Based on the analysis results, we determined the most energy-efficient data rate that can be achieved with acceptable power overhead for each technology node. Also, we identified the optimal clock edge-rate and inter-stage voltage swings in CML gates that achieved minimum transmitter power dissipation. Our analysis results indicate that, when properly optimized, overall transmitter power consumption can be reduced by up to 43% with inter-stage swing optimization with all other design constraints held constant.