Abstract
This paper discusses power-performance optimization for 3-D stencil computing on a stream-oriented FPGA accelerator with highlevel synthesis. Taking a heat conduction simulation and an FDTD electromagnetic field simulation as benchmark applications, powerperformance profiling results are presented focusing on the effect of high-level pipeline parameters. As a result, it is shown that the optimal power efficiency can be achieved basically by optimizing the execution performance. The relationship between power efficiency and the clock frequency is also discussed.
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