Power performance comparison analysis of FPGA using Riemann Definite Integral Equation Solver

Abstract

Definite integral equation solvers were hitherto developed using software which take long time to generate results. The complexity of designs and verifications, due to advancement in calculus and linear algebra, data dependency in designs, and the need for parallelism in models, necessitated the need for faster, accurate, and reliable hardware-based solvers. This will reduce latency and excessive memory requirement in generating values of definite integrals. The Field Programmable Gate Array (FPGA)-Based Definite Integral Solver developed in this research is able to solve definite integral equations with less resource utilization (1.08% look up tables (LUT), 0.07% flip flops (FF), 10.81% digital signal processing (DSP) and 23.86% input-output (IO)) and hence minimum switching activities at lower power (Signals: 0.421W, Logic: 0.345W, Digital Signal Processing: 1.904W and Input/Output: 0.015W) that translates to fast and accurate results generation. The power and resource utilization evaluation on the solver and the performance comparison with similar works showed that excessive memory consumption and resource utilization has been reduced significantly by the design.