Power Optimized Ternary Arithmetic Logic Circuit using Carbon Nano Tube Field Effect Transistor

Abstract

Ternary Logic Circuits have gained the crucial attention of all the semiconductor researchers as it provides better interconnect, power, performance and speed when compared to the conventional binary logics. There is a minimal area overhead in ternary logics but that’s permissible as long as other parameters provide a much beneficial results. Carbon Nano Tube (CNT) Transistors are a remarkable replacement for the conventional Complementary Metal Oxide Semiconductors (CMOS) as they exhibit better electrical connectivity, structural abilities and mechanical properties. The main focus of present-day requirements are designing and developing power optimized high speed circuits without compromising on performance and area. So, to achieve all these, this research work focus on combining both the high-profile techniques to build Low Powered Ternary Arithmetic Logic Circuits (LP- TALCs) using CNT transistors. ALCs plays the major role as the basic operating unit for any processors or circuits which helps to perform arithmetic operations and logic operations in single structure. The various logic operations performed by this TALC circuit is Buffer, Inversion, Ternary NAND, Ternary NOR, Ternary AND, Ternary OR, Ternary Adder, Ternary Subtractor and Ternary Comparator. The structure basically consists of Low Power Enabled Decoder (LPED), Functional modules and Output selection circuit (OSC). LPED circuit helps to achieve low power by enabling the selected circuit operations using decoder circuits and the inputs are fed to functional modules which consists of all the logical structure and finally the output selection circuit consists of encoders which deliver the final output function. The proposed structure is designed using 32nm CNTFET technology and the simulation results shows almost 90% power reduction to their binary counterpart and 85% Power delay product improvement.