Power optimization in configurable ALU using blend of techniques

Abstract

Reduction in power dissipation is an essential design issue in VLSI circuit. One of the important block in any processor is Arithmetic Logic Unit and it performs arithmetic and logical operations. If operations are more and more complex then power dissipation is more. The clock network is a major source of power dissipation so we can reduce significant amount of power if we can gate the clock whenever it isn’t required. From the literature, we have noticed that there several methods/techniques used to reduce the power within ALU, the used methods are moderate and still there is scope to reduce power using blend of techniques. So low power ALU is designed using clock gating techniques besides using PIPO and Booth’s algorithm concept. By giving specific opcode, we can enable the specific operation and other operations are in inactive mode, so we can see less power dissipation in ALU. Low power ALU is having two 8 bit input data with cin, bin, enable and 2 bit shift data and a decoder 4:16 to select the 16 operations by giving 4 bit opcode to it as a input with start enable_function. At each iteration the proposed design is implemented with one of these clock gating techniques i.e latch free clock gated technique, latch based clock gated technique, flipflop based clock gated technique, and synthesis based clock gating technique with parallel in parallel out (PIPO) shift registers. These all techniques are performed with operation selection feature and PIPO shift registers in this design at different operating frequencies 100MHZ, 200MHZ, 400MHZ, 500MHZ and 1GHZ in Virtex-6. Virtex-6 FPGA board having 40nm technology with 1 volt in Xilinx ISE 14.4 tool. This paper mainly focuses to analyze the dynamic power dissipation for various frequencies in ALU with and without clock gating techniques combining with PIPO and Booth’s algorithm methods.