Power management of the autonomous error-tolerant cell

Abstract

This article presents a power management scheme for a new circuit concept - the autonomous error-tolerant (AET) cell - the inner functionality, interconnectivity and reconfiguration of which have been presented earlier. In order to meet reliability and energy efficiency objectives, a special power management strategy and implementation of this strategy are proposed. The power management system consists of power switches, a charge pump for a high voltage generation (for EEPROM cells) and a power management unit (PMU) for regulating and monitoring. The first part of the power management strategy focuses on the functionality of the power management system: we explain the function of power switches and assign design rules for them, propose a solution for high voltage generation, and present the basic blocks and functionality of the PMU. The second part of the strategy concentrates on the power distribution: different power distribution network topologies are used in different regions of the cell. The important aspect when designing the distribution strategy is the effect of power supply noise on the cell performance. Finally, we present the results for power supply noise analysis based on the estimates for silicon area and power consumption in the digital core (DC) of the AET cell in 0.18 /spl mu/m technology.