Towards Generation of a Programmable Power Management Unit at the Electronic System Level

Abstract

Power-awareness is now crucial in the design flow for System-on-Chip (SoC) development. The main objective of power-awareness is to implement a Power Management Strategy (PMS) for the SoC by generating a flexible, yet efficient Power Management Unit (PMU). As the cost of structural changes to a design increases in advanced stages of development, the PMU should be incorporated into the design as early as possible. At early stages, Virtual Prototype (VP) based design at the Electronic System Level (ESL) has become an industry accepted solution. However, existing methods focusing on generating a PMU at the ESL have several drawbacks, such as relying on designers’ domain expertise, a low degree of automation and a lack of programmability.This paper introduces a novel approach that automatically generates a programmable PMU for a given VP at the ESL without the need for prior knowledge about the VP’s structure and behavior. Our approach consists of three main phases: activity pattern extraction, power-aware analysis, and PMU generation. The programmability feature of the generated PMU enables designers to support various target applications. The efficiency and flexibility of the proposed approach are evaluated by the power consumption reduction enabled by the PMU within a real-world VP-based SoC platform.