Power gain performance enhancement of independently biased heterojunction bipolar transistor cascode chip

Abstract

The purpose of this research is to study the power gain performance of an independently biased cascode structure or a new cascode structure (NCS) in comparison to that of a conventional cascode structure (CCS) at 1.9 GHz while investigating the bias conditions. We found that the bias collector current (Ic2) of the common-base (CB) or second-stage transistor is the key factor contributing to the power gain difference between a NCS and a CCS. By employing a monolithic microwave integrated circuit (MMIC) InGaP/GaAs heterojunction bipolar transistor (HBT), simulation and experimental results show that a NCS with higher Ic2 than that of a CCS can offer better power gain performance but less stability compared with a CCS. On the other hand, although a NCS with lower Ic2 than that of a CCS exhibits worse power gain performance compared with a CCS, it can be more stable than a CCS. All of the above indicate that a NCS can deliver superior radio frequency (RF) performance compared with a CCS by setting the appropriate bias conditions.