Power factor correction using an ESP32 embedded in an interleaved boost converter

Abstract

This paper addresses a power factor correction (PFC) approach, employing an ESP32 microcontroller and utilizing an interleaved boost converter as the primary power topology. The issue of low power factor in systems is a critical concern, as it results in increased energy consumption, reduced efficiency, and potential power quality issues. Such problems can be observed in various applications, including industrial machinery, renewable energy systems, and consumer electronics, all of which stand to benefit from an effective power factor correction solution. The proposed system offers several unique advantages and characteristics that set it apart from traditional techniques. First and foremost, the utilization of an ESP32 microcontroller enables increased computational capabilities and flexibility, allowing for advanced control algorithms and real-time monitoring of the system's performance. Secondly, the interleaved boost converter topology enhances efficiency by distributing power among multiple converters, thereby reducing the stress on individual components and minimizing losses. The key aspect of the system's design is the autonomous control of the two converters within the interleaved boost converter, achieved through the implementation of a sliding mode (SM) control strategy that mimics resistive behavior. To enhance the system's stability and performance, a dual feedback loop architecture is incorporated: a swift internal current loop and a slower external loop responsible for regulating output voltage. Promising simulation results validate the effectiveness and robustness of the presented PFC approach. This solution not only addresses the challenges associated with low power factors but also demonstrates the potential for further advancements in the field of power electronics and control systems.