Abstract
The present state of research in the area of low-power design methodologies and mechanisms of power dissipation in digital circuits are considered. The choice of the corresponding model of power estimation is demonstrated to exert a significant effect on quality, cost, and performance of designed digital circuits. An analysis of various power estimation techniques at different levels of abstraction for sequential and combinational circuit design is presented. Special attention is paid to power dissipation analysis of programmable logic devices.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Optoelectronics, Instrumentation and Data Processing
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
