Power efficiency evaluation in Dickson and voltage doubler charge pump topologies

Abstract

This paper presents a theoretical and experimental comparison between two charge pump architectures commonly used in CMOS integrated circuits, namely the Dickson scheme and the cascade of voltage doublers. The comparison is carried out considering power efficiency as the main feature of interest. To compare the two topologies, two charge pumps were integrated in 0.18-μm triple-well CMOS technology. The two charge pumps were designed with the same operating clock frequency, the same storage capacitance per stage, and the same number of stages (and, thus, approximately the same area). The theoretical and the experimental comparison showed that the power efficiency of the voltage doubler scheme is higher (by about 13% at Iout=1mA), mainly thanks to the lower parasitic capacitance associated to the boosted nodes.