Power Dissipation Estimation of CMOS Digital Circuits at the Gate Level in VHDL

Abstract

This paper proposes a static and dynamic power dissipation estimation method of CMOS digital circuits at the gate level. While static power dissipation can be easily estimated by the product of sub threshold leakage current and supply voltage, the dynamic power estimate is obtained by monitoring the switching activity in the circuit and a careful accounting of the parasitic capacitances charge/discharge. A VHDL library was developed to implement the monitoring of leakage currents and switching activity of several circuits (logic gates, encoders, multiplexers, counters) and to estimate their power dissipation. The advantage of using the library is that in early design stages assumptions can be made about the power dissipation of the designed circuit in a target technology. The downside is that the power estimation accuracy depends on the granularity of the structural description that is carried out in VHDL. To verify the estimated power, a finite state machine was implemented with standard logic gates from the 74HC series and its power dissipation was measured. The error between the measured and estimated power is approximately 20%.