Power Control for Crossbar-Based Input-Queued Switches

Abstract

We consider an N × N Input-Queued (IQ) switch with a crossbar-based switching fabric implemented on a single chip. The power consumption produced by the crossbar chip, due to the data transfer, grows as NR3, where R is the maximum bit rate. Thus, at increasing bit rate, power dissipation is becoming more and more challenging, limiting the crossbar scalability for high-performance switches. We propose to exploit Dynamic Voltage and Frequency Scaling (DVFS) techniques to control packet transmissions through each crosspoint of the switching fabric. Our power control operates independently of the packet scheduler and exploits the knowledge of a traffic matrix obtained by online measurements. We propose a family of control algorithms to reduce the power consumption. The algorithms are particularly efficient in nonoverloaded conditions. The actual potential of the proposed approach is also evaluated on a real design case synthesized on a 90 nm CMOS technology.