DVFS Technique on a Zynq SoC-based System for Low Power Consumption

Abstract

This paper analyses the impact on power consumption when the Dynamic Voltage and Frequency Scaling (DVFS) technique is implemented on a SoC Zynq 7000 device. The usage of the DVFS technique allows the hardware IP Core design to reduce the typical power consumption. The main concern is about static and dynamic power consumption reduction by selecting the right CPU clock frequency using the DVFS technique. Several wide-ranging power consumption reduction techniques usually disregard the operating characteristics. Subsequently, we present in this paper, not only the hardware design and the operating characteristics but also the needed measurements for different operation modes to enhance the design for power consumption efficiency. Most of the experiments are conducted on the processing unit, whereas the CPU clock frequency and input voltage for Programmable Logic (PL) systems are altered. The empirical results from the application of the DVFS technique indicate that the worst scenario is when the input voltage supply for PL and CPU clock frequency have the maximum values. The best scenario for this design is when the CPU clock frequency is highest and the input voltage supply for PL is minimal, where the measurements for power consumption, especially for dynamic power consumption show that the value is reduced by additional 3%.