Power aware setup timing optimization in physical design of ASICs

Abstract

Setup timing optimization is a very important and challenging step of the physical design of Application Specific Integrated Circuits (ASICs). Many techniques are available to help the designer to close the design's setup timing. Although, all these techniques have the same objective, which is to resolve the existing setup timing violations, each one has a different power footprint.In this paper, we measured the impact of each optimization technique on power. We ran each optimization transform at different flow stages on a 100 industrial designs from different process technologies. We measured the ratio of Δpower/Δsetup_timing after legalization and global routing to include not only the power added directly by the setup timing optimization, but also the power induced indirectly by placement and global routing perturbation.Experimental results showed that by taking into account the impact on power consumption of each optimization technique, including placement legalization and the global routing, a power reduction of 7.3% on average could be achieved with no timing impact.