Power-area trade-off in power gated FSM synthesis

Abstract

Partitioning and state encoding of FSM is done to minimise power consumption of final power gated circuit. Partitioning of the FSM into two sub-FSMs and then power gating the inactive sub-FSM incorporates some extra circuitry that increases the total area. So, power consumption is minimised, but at cost of increase in area. To get the power and area optimised power gate implemented circuit, we need to check the variation in power and area by varying weights associated with power and area during partitioning and encoding of FSM targeting power gated synthesis and then fix the weights for power and area for power and area optimised FSM synthesis. In this paper genetic algorithm has been used to find the power-area trade off during partitioning and state encoding of FSM for its power gated implementation. The trade-offs has been determined for different boundary depths.