Abstract
To address the performance bottleneck in metal-based interconnects, hybrid optical network-on-chip (HONoC) has emerged as a new alternative. However, as the size of the HONoC grows, insertion loss and crosstalk noise increase, leading to excessive laser source output power and performance degradation. Therefore, we propose a low-power scalable HONoC architecture by incorporating semiconductor optical amplifiers (SOAs). An SOA placement algorithm is developed considering insertion loss and crosstalk noise. Furthermore, we establish a worst-case crosstalk noise model of SOA-enabled HONoC and induce optimized SOA gains with respect to power consumption and performance, respectively. Extensive simulations for worst-case signal-to-noise ratio (SNR) and power consumption are conducted under various traffic patterns and different network sizes. Simulation results show that the proposed SOA-enabled HONoC architecture and the associated algorithm help sustain the performance as network size increases without additional laser source power.
Highlights
As multicore systems-on-chips (SoCs) have become mainstream as chips suffer from diminishing returns of miniaturization and the power wall, a new high-performance on-chip network architecture is needed to overcome the physical limitations of metal interconnects [1,2]
amplified spontaneous emission (ASE) cannot be ignored in physical implementations with contemporary silicon photonics technology, this study focuses on the emerging architecture with a matured manufacturing process that enables feasible on-chip semiconductor optical amplifiers (SOAs), assuming a negligible ASE compared to the cumulated crosstalk noise
The chip size of 16 × 16 hybrid optical network-on-chip (HONoC) is assumed as 1 cm2 and in other cases, the chip sizes are assumed to be proportional to the number of cores
Summary
As multicore systems-on-chips (SoCs) have become mainstream as chips suffer from diminishing returns of miniaturization and the power wall, a new high-performance on-chip network architecture is needed to overcome the physical limitations of metal interconnects [1,2]. A hybrid optical network-on-chip (HONoC) in which the electrical and optical layers are combined, using silicon photonics technology, is emerging as a new alternative for replacing metallic interconnects [3]. The. HONoC uses the optical layer to transmit massive data and uses the electrical layer to send control packets or small-size data. As the number of cores in the system increases, the network-size-scalable architecture is highly desirable. Because of the significant insertion loss in large-scale HONoCs due to the accumulated microring resonator (MR) drops and waveguide crossings, the laser source output power should be increased. As the laser source is the most power-consuming device among
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