Polysilicon Gate Etching in High‐Density Plasmas: Comparison Between Oxide Hard Mask and Resist Mask

Abstract

We have studied the etching of polysilicon gates on a thin gate oxide (4.5 nm) in a high‐density helicon source using a resist mask and an oxide hard mask. Defects can be formed at the edges of the gates when a resist mask is used, showing that the gate oxide has been preferentially etched near the edges of the structures during the process. We demonstrate that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching depends on the polysilicon/oxide selectivity which is shown to be strongly dependent on the presence of carbon in the chamber. The polysilicon/oxide selectivity can be improved by a factor of at least three by using an oxide hard mask in a carbon free chamber. Using an oxide hard mask, very robust polysilicon gate processes can be developed without creating structural defects in the active areas of the devices.