Abstract
A polylithic integration technology is demonstrated for seamless stitching of RF and digital chiplets. In this technology, stitch-chips with compressible microinterconnects (CMIs) are used for low-loss and dense interconnection between chiplets. A testbed using fused-silica stitch-chips with integrated CMIs is demonstrated including modeling, fabrication, assembly, and characterization. A 500 µm-long stitch-chip signal link is measured to have less than 0.4 dB insertion loss up to 30 GHz. A simulated eye diagram for 1000 µm-long stitch-chip signal link has a clear opening at 50 Gbps data rate. Moreover, the S-parameters of the CMIs are extracted from this testbed and show less than 0.17 dB insertion loss up to 30 GHz. Benchmarking to silicon interposer based interconnection is also reported.
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