Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

Abstract

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm2/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.