Abstract
AbstractThe ability to stack nanosheet transistors is an important prerequisite for the realization of vertically monolithic 3D integrated circuits enabling higher integration densities of functions and novel circuit topologies that relax miniaturization constraints. In this respect, a wafer‐scale platform is presented embedding high‐quality nanoscale polycrystalline Ge channels into monolithic metal‐semiconductor heterostructures. Thereto, a fabrication scheme comprising a combination of flash lamp annealing, crystallizing ultra‐thin amorphous Ge nanosheets, and a thermally induced Al‐Ge exchange reaction is demonstrated, facilitating the formation of self‐aligned Al leads enabling sharp Al‐Ge heterojunctions. The high quality of the obtained polycrystalline Al‐Ge‐Al heterostructure nanosheets is confirmed by µ‐Raman, scanning transmission electron microscopy, energy‐dispersive X‐ray spectroscopy, and electron backscatter diffraction measurements. Embedded in back‐ and top‐gate field‐effect transistor architectures, the electrical transport in polycrystalline Al‐Ge‐Al heterostructures is systematically analyzed. Enabling a complementary metal‐oxide‐semiconductor compatible wafer‐scale accessibility of high‐quality polycrystalline Ge with self‐aligned Al contacts, the proposed platform significantly contributes to the development of a broad spectrum of emerging 3D integrated Ge nanodevices.
Highlights
The ability to stack nanosheet transistors is an important prerequisite for the realization of vertically monolithic 3D integrated circuits enabling higher integration densities of functions and novel circuit topologies that relax mini aturization constraints
We present a wafer-scale approach to achieve polycrystalline Ge nanosheets crystallized by flash lamp annealing (FLA) embedded in monolithic Al-Ge-Al heterostructures as formed via a thermally induced Al-Ge exchange reaction
Plasma-enhanced chemical vapor deposition (PECVD) is used to deposit a SiO2 capping layer before FLA is applied to initiate the crystallization of the amorphous Ge nanosheets
Summary
The ability to stack nanosheet transistors is an important prerequisite for the realization of vertically monolithic 3D integrated circuits enabling higher integration densities of functions and novel circuit topologies that relax mini aturization constraints In this respect, a wafer-scale platform is presented embedding high-quality nanoscale polycrystalline Ge channels into monolithic metal-semiconductor heterostructures. Enabling a complementary metal-oxide-semiconductor compatible wafer-scale accessibility of high-quality polycrystalline Ge with self-aligned Al contacts, the digms are placing extraordinary demands on hardware performance and efficiency, which is forcing a shift of research efforts towards the integration of new materials as well as the exploration of tailored device and circuit architectures.[2,3,4] In this respect, proposed platform significantly contributes to the development of a broad low-dimensional Ge structures,[4,5,6] have spectrum of emerging 3D integrated Ge nanodevices. As scaling limitations of the gate length affect these devices likewise to metal-oxide-semiconductor (MOS) FETs, the stacking of such high-speed low-power thin-film transistors on interlayer dielectrics is attractive for the realization of vertically monolithic 3D integrated circuits with higher functional integration relaxing sizing constrains of the individual semiconductor devices.[22,23]
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