Polarization Hysteresis Loops of Ferroelectric Gate Capacitors Measured by Sawyer-Tower Circuit

Abstract

Polarization hysteresis properties of ferroelectric gate capacitors were investigated using a quasi metal-ferroelectric-metal-insulator-semiconductor (MFMIS) capacitor which was constructed by the series connection of a metal-ferroelectric-metal (MFM) capacitor and a metal-insulator-semiconductor (MIS) capacitor. By the polarization-voltage measurement using the MIS capacitor, it was revealed that the difficulty of the polarization hysteresis measurement for ferroelectric gate capacitors is caused by the low response frequency of the inversion region formation. The result indicates that the ferroelectric film in ferroelectric gate capacitors is not fully polarized when the inversion layer is not formed completely. Since the response frequency of the inversion region formation can be increased by illumination, symmetric polarization hysteresis loops could be obtained even in the ferroelectric gate capacitors. The polarization hysteresis loops measured using the MFMIS capacitor agreed well with those calculated by the series connection of MFM and MIS capacitors.