Polarity Balanced Driving Scheme to Suppress the Degradation of $V_{\rm th}$ in a-Si:H TFT Due to the Positive Gate Bias Stress for AMOLED

Abstract

In this paper, we propose a new amorphous silicon (a-Si:H) thin-film transistor (TFT) pixel circuit employing negative bias annealing for active-matrix organic light-emitting diode (AMOLED). This circuit consists of two driving TFTs, four switching TFTs, and two storage capacitors. The new driving scheme adopting negative bias annealing entitled polarity balanced driving (PBD) successfully suppresses the troublesome Vth shift in a-Si:H TFT. The proposed pixel circuit was verified by simulation and fabrication. When a severe electrical bias is applied more than 24 hours and a temperature is increased up to 60 degC rather than a room temperature, the current stability (Iafter_stress/Imax) of the proposed PBD pixel is 0.97 while that of the conventional one is 0.72. Our experimental results show that the proposed PBD can improve a stability of a-Si:H TFT because the applied negative gate bias can successfully suppress Vth shift of the current-driving a-Si:H TFT