PMOS breakdown effects on digital circuits – Modeling and analysis

Abstract

The degradations in the pMOS device due to gate oxide breakdown introduced by voltage stress were investigated experimentally. The stress-induced shifts in gate leakage and I– V characteristics were presented. A combined Verilog-A and sub-circuit model was first time introduced and employed to simulate the pMOS breakdown behaviors. The Verilog-A model can accurately simulate the power law characteristics of breakdown gate leakage current with a fractional coefficient. With the developed model, the simulated results and the measurements have good agreements. The traditional logic circuits, such as the inverter and the latch, have been investigated through Cadence simulations with the improved models. The latch suffers from the gate oxide breakdown significantly. The NULL Convention Logic (NCL) circuit has also been examined and analyzed systematically. The results showed substitute degradations due to the pMOS gate oxide breakdown.