PLL-based clock recovery circuit using ring oscillator

Abstract

This paper describes wide-range phase-locked loop (PLL)-based clock recovery (CR) circuit using voltage-controlled ring oscillator. The CR circuit synchronises the input data for a frequency range of 1 to 10 MHz by changing the length of the oscillator electronically. The hidden clock signal in input data comes out from the oscillator output under synchronised condition. The hardware experimental results confirm the validity of the design algorithm.