PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

Abstract

A cell-based phase-locked loop (PLL) can be realized automatically by a compiler to support up to 1-GHz on-chip clock signal generation. This latest design technology is poised to have an impact on the future VLSI test technology, e.g., as we will demonstrate in this paper that it is useful in the timing circuit for binning the leakage of a TSV in a 3-D IC. Unlike previous delay-line-based leakage binning circuit that could have up to 24% error due to process variation, the proposed PLL-assisted timing circuit is immune to process, voltage, and temperature (PVT) variation and thus can achieve a much higher accuracy.