Plastic chip carrier package

Abstract

Plastic QFP, SOIC packages have been dominant surface mount packages for several years for many of their attractive features like compactness and small form factor. The recent needs are for higher I/O packages, with small form factor has led to many novel packaging schemes like the chip scale package. Currently, the cost of a chip scale package is very high. In addition, the early adoption of a chip scale package technology suffers from the lack of an infrastructure to support it. A lower cost, plastic chip carrier approach is proposed. Although the plastic chip carrier may not always fit the rigid definition of a chip scale package (i.e. package area of less than 1.2 times the die area), it does have a smaller footprint than conventional molded packages with the same body size and pin count; it may also have a lower cost structure associated with it due to its simplified assembly. In addition, the chip carrier package in this design would not have lead coplanarity issues associated with it like other conventional surface mount packages. This paper will discuss proposed construction details of this packaging scheme. Issues like the reliability and performance of this package are important considerations, they need to be evaluated but will be addressed in later evaluations.