Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

Wu-Te Weng,Yao-Jen Lee,Tiao-Yuan Huang,Horng-Chih Lin

doi:10.1155/2009/308949

Abstract

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventionalSiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Highlights

Researchers first reported plasma-induced damage (PID) in 1983 [1] using the plasma steps during the interconnect formation processes
Vst or Est is able to generate lots of defects in high-k/metal gate transistors [16]. These PID effects can aggravate the degradations of the dielectric layer owing to the extra damage current paths generated by the Vst across the dielectric layers during the plasma processing
For high-k/metalgate transistors, the damage current breaks the bonds of Hf-based dielectric and produces more oxygen vacancies to enhance the instability of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI)

Summary

Introduction

Researchers first reported plasma-induced damage (PID) in 1983 [1] using the plasma steps during the interconnect formation processes. PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability [2]. The silicon wafer manufacturing employs many plasma-processing steps, including gate electrode etching [3], high-density plasma chemical vapor deposition (HDP-CVD) [4], metal interconnect etching [5], and photoresist ashing [6]. Charges (i.e., ions or electrons) accumulated from a large interconnect area cause a local imbalance in the surface potential across the gate dielectric and cause current to flow through the gate electrode. The plasma damage current can potentially break the gate dielectric bonds with increasing gate dielectric leakage current or decreasing breakdown voltage. The defects or weak points that PID creates in the bulk dielectric and the dielectric/Si-substrate interfaces can further degrade the transistor reliability after reliability stressing

Methods

Results

Conclusion