Abstract
Plasma charging effects on a sub-0.5 /spl mu/m CMOS process with 90 /spl Aring/ gate oxide and triple layer metal was studied for plasma induced damage with diode and ESD protection schemes. The n and p channel transistors in a CMOS driver enabled discharging of positive and negative charges using the source-drain region as diodes. This study also showed that the p channel devices are more sensitive to plasma charging than n channels. The diode protection provided to the transistor gate reduced the magnitude of plasma process induced damage, but a large antenna ratio on protected gates was observed to produce measurable shifts in V/sub t/ and I/sub dsat/.
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