Identification of plasma induced damage conditions in VLSI designs

Abstract

Typically, the plasma charging effect is investigated by using test structures that do not replicate conditions occurring in real VLSI ICs well enough. Consequently, understanding, modelling and detection of plasma charging induced gate oxide damage in real ICs is often inadequate. This paper discusses a new plasma charging monitoring technique that assesses the extent of this problem. This technique employs a multiplexed monitoring (MAM) test structure with more than 400 configurations in order to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35 /spl mu/m, 75 /spl Aring/ gate oxide CMOS technology. The obtained results lead to a new definition of antenna ratio which is proposed to capture plasma charging conditions in real VLSI devices.