Plasma deposited SiO2 for planar self-aligned gate metal–insulator–semiconductor field effect transistors on semi-insulating InP

Abstract

Metal–insulator–semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700–1000 Å gate insulator of SiO2 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 °C, 5 W, and power density of 8.5 mW/cm2. High frequency capacitance–voltage measurements were taken on MIS capacitors which have been subjected to a 700 °C anneal and an interface state density of 1×1011/eV cm2 was found. Current–voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 1014 Ω cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 °C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 μm. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1×103. This is the first reported viable planar InP self-aligned gate transistor process reported to date.