4H-SiC MIS Capacitors and MISFETs With Deposited $\hbox{SiN}_{x}/ \hbox{SiO}_{2}$ Stack-Gate Structures

Masato Noborio,Jun Suda,Tsunenobu Kimoto

doi:10.1109/ted.2008.926644

Abstract

SiN x / SiO 2 stack-gate structures, followed by N 2 O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N 2 O at 1300degC. When the MIS capacitor with a SiN x / SiO 2 thickness of 10 nm/50 nm was annealed in N 2 O for 2 h, the interface trap density at E c - 0.2 eV is below 1 X 10 11 cm -2 eV -1 . Oxidation of SiN x during N 2 O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiN x / SiO 2 stack-gate structure annealed in N 2 O demonstrate a reasonably high channel mobility of 32 cm 2 / V ldr s on the (0001)Si face and 40 cm 2 / V ldrs on the (0001) C face.

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