Abstract

To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.

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