Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

Abstract

Monolithic 3D is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias (TSV). In this paper we demonstrate that a modified 2D placement technique, coupled with a post-placement partitioning step, is sufficient to produce high quality monolithic 3D placement solutions. We also present a commercial router based monolithic inter-tier via (MIV) insertion methodology that dramatically improves the routability of monolithic 3D-ICs. We develop a routing demand model for monolithic 3D-ICs, and use it to develop an O(N) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product (PDP) by up to 4% and 4.33% respectively, under the same half-perimeter wirelength. This allows a two-tier monolithic 3D-IC to achieve, on average, 19.2% and 12.1% improvement in routed wirelength and PDP over 2D, even with reduced metal layer usage.