Pixel-level continuous-time analog signal processing for 130 nm CMOS MAPS

Abstract

In this work a different approach is proposed to signal processing in CMOS monolithic active pixel sensors (MAPS). A deep N-well is used as the charge collecting electrode while a classical processing chain for capacitive detectors is used to shape the charge signal. This solution, which takes advantage of the triple well option available in modern deep CMOS submicron processes, is compatible with architectures performing data sparsification at the pixel level. In this work selected data from the characterization of the first deep N-well MAPS prototype, Apsel0, and of the successor chip, Apsel1, will be presented.