Pipelined architectures for the Viterbi algorithm

Abstract

The main part of the Viterbi algorithm is a nonlinear feedback loop which presents a bottleneck for high-speed implementations. We propose four different solutions for increasing the computation speed of the Viterbi algorithm, three of them are based on the utilization of pipelined systems combined with efficient scheduling methodologies and the other one is based on the simplification of the ACS recursion to cut down the critical path of the system.