Minimized method Viterbi decoding: 600 Mbit/s per chip

Abstract

The Viterbi algorithm is a common application of dynamic programming in communications. Since it has a nonlinear feedback loop, this loop is the bottleneck in high-data-rate implementations. It is shown that asymptotically the loop no longer has to be processed recursively, i.e. there is no feedback (resulting in negligible performance loss). This can be exploited to derive a purely feedforward method for Viterbi decoding, called the minimized method. It is demonstrated that the minimized method can be implemented very efficiently by a systolic architecture. This is shown on a chip design which achieves 600-Mb/s decoding speed per chip, for a K=3 convolutional code. By designing one cascadable module (chip), any speed up can be achieved simply by linearly adding modules to the implementation. >