Abstract
Pinch-off voltage (Vp) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed Vp becomes smaller than the ideal Vp while maintaining a linear relationship with the gate–source voltage (Vgs). The device simulation analysis revealed two mechanisms for Vp lowering. One is current saturation due to the increase in onset gate–drain voltage (Vgd), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with Vgs. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing Vp lowering.
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