Physics-based simulation of stress-induced and electromigration-induced voiding and their interactions in on-chip interconnects

Abstract

A novel physics-based simulation model of electromigration (EM) and stress-migration (SM) induced degradation of electrical characteristics of on-chip interconnects is developed based on the coupled evolution of stress and voiding resolved by means of finite element simulations (FEM). The void evolution tracked with the phase field methodology, is linked with the evolution of EM/SM induced stress, which are generated in the metal segments by the interaction of the inelastic deformations due to divergences of atomic fluxes with the rigid confinement. Accounted atomic exchange between the metal and void surface removes a limitation on the void volume conservation. Developed simulation methodology allows to predict effects of the metal segment architecture and geometry, metal morphology and texture, as well as atomic diffusivities along the variety of migration venues on voiding-induced degradation of interconnect electrical conductance. Results of performed simulation indicate that the pre-existed stress induced voids (SIV) can evolve under the action of applied electric current and affect interconnect reliability. The developed physics-based simulation methodology can help to address reliability concerns by optimizing the properties of interconnect materials and modifying the physical design of the interconnect layouts in order to achieve EM resistant on-chip interconnects.