Physical-design-friendly hierarchical logic built-in self-test—A case study

Abstract

This paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design. The design consists of two embedded cores, each containing approximately 45 million primitives and 2.5 million flip-flops. The implemented architecture supports an at-speed staggered launch-on-capture clocking scheme and includes novel features to reduce turnaround time during engineering change order (ECO) and the device's BIST runtime. It also embeds test and diagnosis features to facilitate debugging of the device at the system level. The BIST hierarchy includes wrappers surrounding each core with access from chip-top allowing for both parallel and serial validations of the cores. This case study successfully demonstrates the feasibility of using the implemented features for speedy ECO, synergy with physical design flow, and ease of test and diagnosis.