Physical timing models of small-geometry CMOS inverters and multi-input NAND/NOR gates and their applications

Abstract

Physical timing models for small-geometry CMOS inverters and multi-input NAND/NOR gates have been developed. In the model formulation, the rise/fall time interval of the gate output voltage is divided into two regions according to the operating region of each MOSFET. The complete large-signal equivalent circuit is then constructed and linearized. By using the Modified-Dominant-Pole-Dominant-Zero method, the effective dominant pole in each region is found and the waveform function of the output voltage is approximated by a single-pole response. Finally, rise/fall times and delay times are formulated. As compared with SPICE simulation and experimental results, the maximum error of the developed timing models is 15% for CMOS inverters and multi-input NAND/NOR gates with different channel dimensions, capacitive loads, device parameters and input excitations. Application examples have been presented to demonstrate the efficiency of the developed timing models in timing verification and logic hazard detection. Moreover, based upon the time models, it is seen that a quasi-constant-voltage scaling law has an optimal figure of merit combining speed, area and reliability. In addition, the optimal width ratio of small-geometry CMOS inverters depends on the ratio of effective channel modulation factors rather than the mobility ratio. Reasonable accuracy, less CPU time and memory requirement, and wide applicable ranges make the developed timing models quite feasible in many applications.