A new interconnection delay model considering the effects of short-channel logic gates

Abstract

A modeling approach to calculate the rise, fall, and delay times for short-channel CMOS inverters with interconnection lines is presented. Extensive comparisons between model calculations and SPICE simulations have shown that the analytic model has a maximum error of 16% on the delay times for CMOS inverters with interconnections of different gate sizes, device parameters, and even input excitation waveforms. Reasonable accuracy, wide applicable range, and high computation efficiency make the developed timing models quite attractive in MOS VLSI timing verification and automatic sizing. >