Physical failure analysis in semiconductor industry—challenges of the copper interconnect process

Abstract

Since the copper interconnect dimensions shrunk continuously, physical failure analysis becomes increasingly important for process optimization. Failure localization and defect analysis in interconnect structures as well as analysis of barrier/seed step coverage are challenges of the copper inlaid technology. Failure localization in via chain test structures using voltage contrast analysis with SEM/FIB tools and OBIRCH and subsequent destructive failure analysis using FIB/SEM and TEM are described. The inspections of voids in copper interconnects and of buried residuals in vias are typical tasks for process monitoring, which make the application of leading-edge analytical techniques necessary. Barrier/seed step coverage analysis at via chains challenges both TEM sample preparation and analysis. 3D object reconstruction by electron tomography is a promising future method for this task.