Abstract
Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.
Highlights
The last decade has seen Si-photonics promoted as a platform for potentially revolutionary advances in the fields of Telecommunications, Data Communications, Medical Technology, Security, and Sensing [1,2,3]
(photonic integrated circuit) packaged with with a multi-channel quasi-planar planar coupled (QPC) fiber‐array, a hybrid‐integrated laser based sourceon based on a micro‐optic bench coupled (QPC) fiber-array, a hybrid-integrated laser source a micro-optic bench (MOB), (MOB), a vertically integrated electronic integrated circuit (EIC), and a thermo‐electric cooler
Edge‐coupling is a well‐established approach for the commercial packaging of laser‐chips [16], but has not been widely adopted in the field of Si‐photonics, despite being able to deliver broadband, coupler for a Si‐photonic integrated circuits (PICs) consists of an inverted taper embedded in an integrated nitride‐based spot‐size‐converter (SSC), or a post‐process deposited polymer‐based SSC, to increase the effective mode‐field diameter (MFD) of the on‐PIC waveguide mode to approximately 3 × 3 μm [18,19]
Summary
The last decade has seen Si-photonics promoted as a platform for potentially revolutionary advances in the fields of Telecommunications, Data Communications, Medical Technology, Security, and Sensing [1,2,3]. While satisfyingany anyone oneofofthese these photonic packaging requirement be trivial, especially the tools and resources a laboratory environment, they can becan difficult to realize in a robust, stand‐. With the tools and resources a laboratory environment, they be difficult to realize in a robust, alone device for prototyping in the field This is especially the case in more advanced photonic stand-alone device for prototyping in the field. Devices, wherethere thereisisthe the simultaneous need for several different varieties of packaging, i.e., channel coupling, a vertically integrated driver‐chip, and a high‐speed connection, and multi-channel Fiber-to-PIC coupling, a vertically integrated driver-chip, and a high-speed connection, a thermo‐electric cooler [12]. This article provides a review of the different optical, electrical, and thermal considerations for successful photonic packaging, as a PDR ‘primer’.
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