A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4x4 Optical Mesh

Abstract

As we envision post-Moore solid-state circuits, there is a growing impetus for leveraging emerging device technologies outside the traditional CMOS fold. Silicon photonics (SiP) fabrication in CMOS-compatible foundries has emerged as an enabler for high-performance optoelectronic systems, where the complementary strengths of electronics and photonics solve long-standing challenges in either of the two fields. Foundry-based multi-project wafer (MPW) fabrication has resulted in Moore's law of silicon photonics where the number of components on a chip doubles every 12-to-18 months [1]. However, photonic integrated circuit (PIC) designers undertake long design cycles that involve simulation, layout, fabrication, packaging, and testing, which incurs significant engineering effort and cost. A general-purpose reconfigurable PIC will allow for rapid design exploration that can revolutionize PICs by replicating the success of electronic field-programmable gate arrays (FPGAs). Recently, reconfigurable PICs that utilize square and hexagonal meshes have demonstrated reconfigurable optical circuit functionality [2–5]. However, these small-scale PICs were either fabricated using a non-foundry e-beam lithography or a passive silicon-based platform. The state-of-the-art design consisted of 7 mesh cells that fit 20 distinct functionalities [4]. Challenges with reconfigurable PIC architectures include process and temperature (P/T) variation, thermal crosstalk, and packaging [6].