Phase margin measurement for power factor correction circuits in electronic ballasts

Abstract

The use of power factor correction circuits (PFCC) in electronic ballasts over a wide range of operating conditions has been increasing. The stability of the PFCC over such broad operating regions is sometimes questionable. Therefore, it is important to measure the relative stability of the PFCC to insure proper operation. To determine the relative stability of a PFCC, a method is developed to measure the phase margin of the open loop circuit. By using a properly placed transformer, a small signal can be injected into the control loop. The phase margin can then be determined from voltages measured at the terminal of the transformer. The phase margin for a typical circuit is measured over a wide range of operating conditions. Results of these measurements are compared to calculated phase margins based on linearized models of the system. The comparison shows similar results but with enough differences to justify the need to determine the phase margin experimentally.