Phase Field Simulation of Electromigration-induced Failure in TSV Interconnect

Abstract

Nowadays, the innovation of microelectronic technology calls for the development of 3D packaging. Meanwhile, Through-Silicon-Vias (TSVs), as an important developing technology, have enabled cutting-edge technologies for 3D packaging. However, electromigration (EM) has been a long-standing concern for the development and further application of the TSV-based interconnects. Metal transport caused by EM may lead to local damage or even open circuit failure. There are two types of EM damages, i.e., voids and slits. The evolution of those damages is significantly influenced by two fast micro pathways, which are the grain boundary (GB) and the phase interface. Therefore, to simulate the EM-induced failure caused by slits and voids, the influence from microstructures, in particular the grain structures, need to be investigated. Here, we utilize the phase field method to simulate the EM-induced failure process of trapezoidal Cu-TSVs with polycrystalline structures. The formation of slits due to the GB grooving, the interfacial diffusion, and the migration and deformation of voids are observed. Eventually, the fusion between slits and voids results in the open circuit failure of the TSVs. In addition, the results show that increasing the number of grains in the TSV exerts an adverse effect on the failure process. In particular, when the current flows downwards and more grains contact the bottom end of the TSV, the failure process can accelerate significantly.