Electromigration Studies on 6 µm Solid Cu TSV (Via last) in 32 nm SOI Technology

Abstract

Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration is maturing, reliability is a key parameter to be studied. One such reliability wear-out mechanisms is electro-migration (EM). In this paper, we report on experimental electromigration studies of TSVs used in 3-Dimensional integration (3Di). While TSV themselves can carry large currents, the connection to on-chip wiring -- so called capture levels on both sides of the thinned die are the weakest link from an EM perspective. EM performance of the TSV element itself, the TSV/capture level and TSV/redistribution level (RDL) is investigated using dedicated structures with the respective elements as the weakest link. 300mm 3Di wafers were used using a 32 nm CMOS process with a 6 µm solid Cu TSV integrated at the fat wire levels and our results suggest that this integration scheme exhibits robust EM performance. With the right capture metallizations on both sides of the TSV, we estimate a DC current of 1A per TSV can be sustained for a 10KPOH product. Design methodologies to further improve and better redistribute the current to improve EM performance will be presented.